Axes de recherche
Real-time systems are defined as those systems in which the correctness of the system depends not only on the logical correctness of result of computation, but also on the time on which results are produced. If the response time violates the timing constraints imposed by the dynamic of the environment, the system has to pay a cost for the violation. Hence, it is essential that the timing constraints of the system are guaranteed to be met. The cost of failure in a real-time system differentiates real-time systems into mainly three types of real-time systems: Hard, Soft and Firm. In my research I am interested in Hard and Soft real-time systems.
Energy consumption is an increasing concern in cyber-physical real-time systems, especially when processing elements operate on battery power. Embedded real-time distributed systems must support increasingly complex applications such as distributed video surveillance, processing a large amount of sensor data, etc. The energy consumption can be optimized in recent processor by the mean of DVFS (Dynamic voltage and Frequency Scaling), and DPM (Dynamic Power Management). The first allows to calibrate the operating frequency to reduce the dynamic energy. In DPM, the processor (core) static energy may be reducing by "switching off" some processor components such as clocks. Reducing the frequency and changing processor mode affects the processor performances by increasing the execution time and reducing the processor capabilities.
I focus on how to use such techniques to reduce the energy consumption while guaranteeing the respect of all timing constraints, on platforms similar to ARM big.LITTLE.
A recent trend in hardware architecture design is to combine high performance multi-core CPU hosts with a number of application-specific accelerators (e.g. GPUs, DLAs, FPGAs, ...) in order to support complex real-time applications with machine learning and image processing software modules. Such application specific processors are defined by different levels of programmability and a different Instruction Set Architecture (ISA) compared to the more traditional SoCs, such as in the integrated version of the NVIDIA Volta architecture within the NVIDIA Xavier SoC where several ARM cors are embeded with GPUs, DLAs, PVAs.
I am interested in analyzing the timing behavior of a real-time application as they represent drastic differences at the level of ISAs, preemption capabilities, memory hierarchies and inter-connections. We develop a platform to validate our research and to reduce the effort when programming such platform by generating automatically the prototypes of source codes.
Many modern GPOS (General Purpose Operating Systems) kernels provide real-time scheduling support for time sensitive applications. For example, Linux provides three real-time scheduling policies: SCHED_FIFO and SCHED_RR which are based on fixed priorities and are standardized by POSIX; and SCHED_DEADLINE , which provides resource reservation on top of Earliest Deadline First (EDF). Thanks to the temporal isolation property, the latter is particularly useful when mixing real-time and non real-time workloads in the same system. These scheduling policies are highly configurable, and can be used to implement either global scheduling or partitioned scheduling by properly set the tasks' CPU affinities or using the cpuset mechanism. In global scheduling, load balancing is implicite however as tasks are arranged in a single queue, they are allowed to migrate, thus generating an overhead due to migrations.
I investigate load balacing techniques for partitioned scheduling by allowing permannent and temporary migrations without breaking the temporal isolation.
The evolution and development of semiconductor technology has made possible the integration of billions of transistors on a single chip. With this technological explosion, designers are able to develop Integrating Complex (ICs) functional elements into a single chip, known as a Multi-Processor System-on-Chip (MPSoC). The first-generation MPSoCs used buses to allow information exchange between components. With the increase of PEs in a single chip, the bus is highly contented, which limits the scalability and becomes quickly a bottleneck for high performances. Networks on-Chip (NoC) has been proposed as an alternative solution for scalable interconnection between PEs and power efficiency.
In a typical real-time system, several tasks are in concurrence on different resources and are subject to share data. When executing real-time tasks on a NoC-based architecture, the shared data has to be routed between the computing units where communicating tasks are allocated. The needed time to route data from its source to its destination is called communication latency. Latency has to be bounded to ensure that each task instance has been executed without violating the real-time constraints (no later than its deadline). NoC components (routers and network interfaces, ...) are designed to maximize network utilization without taking into account predictability and temporal behavior of communications, thus they are not suitable to real-time systems.
The goal of research I lead in this topic is to bound latency by including additional components onto routers in the goal of : (i) considering the urgency of a real-time communication, (ii) reduce the worst case latency bounds (iii) without sacrificing the performances of non-real-time task using the less possible architectural modifications.
In 2D-mesh NoCs, tiles are arranged in a grid such that typically each tile has 4 neighbors: left, right, north and south. This topology is simple to implement and easy to manage compared to more complex topology. Thus, it receives more attention in NoC research community. Nevertheless, when the network traffic is very high, network performance can drastically fall because of the contention and congestion that may be generated in frequently used routers (central ones). In a general 3D package system, two or more SoCs are stacked vertically so that they occupy less space and/or have greater connectivity. Such techniques have been applied onto NoC architectures by overlaying two or more 2D NoCs on the same SoC allowing shortening communication path compared to a 2D NoC architecture however as communication medias are physically overlaid they may be a source of heating, hence failure.
I participate in this project by including formal methods to analyze the behavior of 3D NoCS compared to 2D NoCs and by defining at design time, the most appropriate communication media disposals to provide real-time guarantees.